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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:43:00 11/20/2011 
-- Design Name: 
-- Module Name:    MEM_CTRL - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.global_definition.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MEM_CTRL is
	port	(
				OP    : in  std_ulogic_vector(5 downto 0) := "000000";
				MEMOP : out std_ulogic_vector(1 downto 0) := "00"
			);
end MEM_CTRL;

architecture Behavioral of MEM_CTRL is
begin
	process(OP)
	begin
		case OP is
			when OP_LW | OP_LW_SP   =>
				MEMOP <= MEMOP_READ;
			when OP_SW | OP_SW_RS | OP_SW_SP | OP_INT1 | OP_INT2 =>
				MEMOP <= MEMOP_WRITE;
			when others => 
				MEMOP <= MEMOP_NONE;
		end case;
	end process;

end Behavioral;

